1. Field of the Invention
The present invention generally relates to the design and testing of semiconductor chips and integrated circuits, and more particularly to a method of modeling soft errors in a logic circuit that arise from, e.g., an alpha-particle strike.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A digital microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells, memory cells and input/output (I/O) cells.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files arc then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern one or more dies on a silicon wafer using a sequence of photolithographic steps.
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the deep-submicron regime, it is becoming increasingly important for the performance and reliability of IC chips and systems to understand the effects of soil errors that might arise from stray radiation or electrostatic discharge. For example, a soft error may occur when an alpha particle hits the diffusion regions of a metal-oxide semiconducting (MOS) transistor of a logic circuit and produces a charge that leads to a faulty transition. Alpha emissions are fairly common from the lead in C4 solder that is used for IC interconnects. In a modern MOS transistor, the gate terminal is a layer of polycrystalline silicon separated from a channel of n-type or p-type semiconductor material (silicon or a mixture oaf silicon and germanium) by a thin insulating layer of silicon dioxide or silicon oxynitride. When a voltage is applied between the gate and source terminals, the generated electric field penetrates through the insulating layer and creates an inversion channel which provides a conduit for current flow. An alpha-particle strike at or near the gate terminal can thus affect the applied voltage and change the conducting state of the transistor (a single event upset or SEU).
This effect may be more pronounced with a silicon-on-insulator (SOI) MOS transistor. SOI technology provides a silicon substrate carrying an insulating silicon dioxide layer below a layer of silicon in which the individual field effect transistors are formed by source and drain regions of doped silicon of one polarity separated by a body (channel) of doped silicon of the opposite polarity. A primary benefit of an SOI MOS transistor is the reduced capacitance of the switch, so it operates faster. However, the body region of each individual SOI transistor is electrically insulated from its underlying silicon substrate, so electrical charging of the body is more likely with SOI technology.
A change in the state of a device caused by radiation or electrostatic discharge will only generate an error in the logic circuit if it propagates to a latch or storage element prior to the clock arrival (sampling) time. Nevertheless, many SEUs lead to soft errors in IC chips and computer systems, and the soft error rate (SER) associated with combinational logic is steadily growing. New methodologies are thus needed to ensure circuit reliability by characterizing the events leading to soft errors. One approach to this problem is the use of technology computer-aided design (TCAD) field solvers to simulate the operation of a device as it undergoes an alpha-particle strike through the gate. While field solvers provide useful analytical results, they are very complex to set up and computationally intensive to carry out.
Another approach to modeling the creation of soft errors uses a circuit-level simulation tool such as SPICE which employs numerical integration formulae to form companion models for circuit elements at successive points in time. SPICE uses a netlist file that contains a description of the circuit with appropriate resistance, inductance and capacitance values corresponding to respective nodes as well as nonlinear devices such as transistors or diodes. An analysis is performed at an initial time, the tile variable is then incremented, and an analysis is performed at that next time step, with the process repeating until the final time step is reached. One example of a SPICE-type simulator is described in U.S. Pat. No. 6,928,626.
The alpha-particle strike can be modeled as a current source, as illustrated in FIGS. 1A and 1B. FIG. 1A shows one model 2 wherein a current source 4 is inserted between the drain and source terminals of a device 6 with a floating body. FIG. 1B shows another model 8 wherein the current source 4 is inserted between one of the source or drain terminals and the body of device 6. During the simulation, a current pulse of increasing amplitude is repeatedly injected via current source 4 to simulate alpha-particle strikes until the device changes its logical state (e.g., turns on). The current pulse can be integrated over time to compute the critical charge (QCRIT) that was necessary to cause the upset. A similar hardware technique which adjusts the current pulse amplitude and duration to find QCRIT is disclosed in U.S. Pat. No. 6,330,182.
Circuit simulators such as SPICE are straightforward and fairly quick to run, but they still have significant drawbacks in modeling the circumstances of soft errors. The choice of where and how to inject the current pulse affects simulation accuracy, and if the simulation is not set up properly the results can be inaccurate. It is also impossible to adjust the simulation to take into consideration certain variations in device fabrication such as different source and drain resistances. It would, therefore, be desirable to devise an improved method of simulating soft errors in a logic circuit which could provide a relatively quick analysis with greater accuracy for realistic device parameters. It would be further advantageous if the method could easily be integrated into a design automation tool.